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SPL31A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3. FEATURES.................................................................................................................................................................................................. 3 4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 4 5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5 5.1. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 5 5.2. ROM AREA ........................................................................................................................................................................................... 5 5.3. OPERATING STATES ............................................................................................................................................................................... 5 5.4. TIME-BASE-SETTING REGISTER ............................................................................................................................................................. 5 5.5. TIMER/COUNTER ................................................................................................................................................................................... 6 5.6. SPEECH AND MELODY............................................................................................................................................................................ 6 5.7. LCD CONTROLLER/DRIVER.................................................................................................................................................................... 6 5.8. VOLTAGE DOUBLER/REGULATOR ............................................................................................................................................................ 6 5.9. PWM OUTPUT....................................................................................................................................................................................... 6 5.10. LOW VOLTAGE RESET ......................................................................................................................................................................... 6 5.11. WATCHDOG TIMER (WDT)................................................................................................................................................................... 7 5.12. LOW VOLTAGE DETECT ....................................................................................................................................................................... 7 5.13. MASK OPTIONS................................................................................................................................................................................... 7 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 8 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 8 6.2. DC CHARACTERISTICS (VDD = 3.0V, TA = 25) ................................................................................................................................... 8 6.3. DC CHARACTERISTICS (VDD = 4.5V, TA = 25) ................................................................................................................................... 8 6.4. THE RELATIONSHIPS BETWEEN THE ROSC AND THE FCPU ........................................................................................................................... 9 6.5. THE RELATIONSHIPS BETWEEN THE FCPU AND THE IOP .............................................................................................................................. 9 6.6. THE RELATIONSHIPS BETWEEN THE FCPU AND THE VDD........................................................................................................................... 9 7. APPLICATION CIRCUITS......................................................................................................................................................................... 10 8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 11 8.1. PAD ASSIGNMENT ................................................................................................................................................................................11 8.2. ORDERING INFORMATION ......................................................................................................................................................................11 8.3. PAD LOCATIONS.................................................................................................................................................................................. 12 9. DISCLAIMER............................................................................................................................................................................................. 13 10. REVISION HISTORY ................................................................................................................................................................................. 14
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AUG. 10, 2001 Version: 1.2
SPL31A
64KB LCD CONTROLLER/DRIVER
1. GENERAL DESCRIPTION
The SPL31A, an 8-bit CMOS single chip microprocessor, contains RAM, ROM, I/Os, interrupt/wakeup controller, timer, 8-bit PWM audio output and automatic display controller/ driver for LCD. With a dual channel PWM driver, attractive sound effects can be generated easily. Built-in voltage doubler and voltage regulator Furthermore, a provide robust and adjustable (16-level) LCD supply voltage to get the best display quality for specific panels. saving. software controllable standby mode is also implemented for power The SPL31A is designed with state-of-the-art technology to fulfill the requirements of LCD applications especially for hand-held products.
3. FEATURES
! Built-in 8-bit CPU 160 bytes SRAM 64K bytes ROM Max. CPU clock: 3.0MHz @ 2.4V - 5.5V Programmable CPU clock frequency, 1/2, 1/4, 1/8, 1/16, 1/32 or 1/64 of R-oscillator's clock frequency is available Provides 7 interrupt sources ! Built-in 8-bit 2-channel PWM outputs ! Built-in 32.768KHz Crystal / R-oscillator Crystal or R-oscillator (mask option) Crystal oscillator switches from strong to Weak mode automatically Internal time base generator
2. BLOCK DIAGRAM
ROSC 32.768KHz
! Built-in System R-oscillator Only one resistor is needed ! Two 16 bits timer/counters ! Low Voltage Reset / Low Voltage Detect
Interrup/wakeup Control
PWM
32.768KHz Oscillator & Time Base
AUDP
Provides 2.3V low voltage reset function 2.4V/2.6V low voltage detect (Mask option)
Low Voltage Reset Two 16-bit Auto Reload Timers
AUDN
! Low power consumption Operating current: 1.0mA/1.0MHz @ 3.0V Very low standby current : ISTBY < 1.0A @ 3.0V In standby mode: stop all oscillators ! Max. 12 general purpose I/O SEG[43:41] can be optioned to IOEF[7:5]
64K bytes ROM
IOCD3 - 0 (I/O) 9 I/O ports
160 bytes RAM
8-bit RISC Processor
LCD RAM 44 Segments X 5 Commons LCD Driver
IOEF4 - 0 (I/O)
8 IO pins support Key wake-up mode ! LCD controller / driver 44 segments x 5 commons, max. 220 dots Programmable bias option (1/2,1/3 bias) and duty option (1/2,1/3,1/4,1/5 duty) Built-in voltage doubler and regulator to generate VLCD voltage for LCD driver Adjustable 16-level VLCD for various panels 1/3 bias: VLCD (3.0V - 6.0V) 1/2 bias: VLCD (2.0V - 4.0V)
COM4 - 0
SEG43 - 0
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SPL31A
4. SIGNAL DESCRIPTIONS
Mnemonic SEG43 - 0 COM4 - 0 IOEF1 - 0 IOEF4 - 2 IOCD3 - 0 ROSC RESET AVDD AUDP AUDN AVSS X32I X32O TEST VDD VSS VLCD VDD1 VDD2 CUP1 CUP2 PIN No. 5 - 48 49 - 53 74 - 73 3-1 68 - 65 63 62 71 70 72 69 61 60 59 4 64 54 55 58 56 57 I Charge pump capacitor interconnection pins for LCD voltagegeneration I/O I I P O O P I O I P P I I I/O port System R-oscillator input, connect to VDD through resistor System reset input PWM power supply input PWM audio output PWM audio output PWM ground input 32.768KHz crystal input, or connect to VDD through resistor as R-oscillator input (Mask option) 32.768KHz crystal output Test mode input Power supply voltage input Ground input LCD voltage, connect to VSS through a capacitor Connect coupling capacitors for charge pump Type O O I/O LCD driver segment output LCD driver common output I/O port (provide key wake-up function) Description
Note1: Legend: I = Input, O = Output, P = Power Note2: SEG43 - 41 can be optioned to IOEF7 - 5, IOEF7 - 0 provide key wake-up function Note3: Provides 220 bits read/writable LCD RAM buffer Note4: 32.768KHz Crystal oscillator can be optioned to R-oscillator (connect to VDD through resistor).
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SPL31A
5. FUNCTIONAL DESCRIPTIONS
5.1. Map of Memory and I/Os
*I/O PORT: * MEMORY MAP $0000 I/O & Registers $001F $0020 $003D $0060 * NMI SOURCE: SRAM $00FF reserved $0200 Test Program $05FF $0600 Program ROM Bank #0 $7FFA $7FFF LCD RAM Buffer reserved
state is entered by writing the SLEEP register ($09).
There are
IOCD Port $0004 IOEF Port $0005
* I/O CONFIG
four wake-up sources in SPL31A: port IOEF wake-up, TIMR0 wake-up, 4Hz/8Hz/ 16Hz/32Hz wake-up and 2Hz/1Hz wake-up. If any wake-up event occurs, execution of the next instruction continues in the operating state. states. In standby mode, all modules By writing will be shut down, and RAM and I/Os remain in their previous Therefore current consumption is minimized. to SLEEP register but keeps 32768 oscillator running, the system is in HALT state. CPU clock is halted while it waits for an event (key press, timer overflow) to generate a wake-up in HALT state. The 32768 related modules (timer/counter, LCD driver...) may remain active in the halt state. for the SPL31A.
Write to SLEEP register, 32768 oscillator OFF OPERATING Wake-up or user reset
, ter gis re N P rO EE ato SL ill to osc rite 68 W 327 et es rr se
IOCD_Config $0000 IOEF_Config $0019
INT1 ( from TIMER 1 )
* INT SOURCE
INT0 ( from TIMER 0 ) INT1 ( from TIMER 1 ) T16Hz ( 4Hz /8Hz /16Hz /32Hz ) T2Hz ( 2Hz /1Hz ) 128Hz 2KHz EXTINT ( from IOCD0 pin )
* WAKEUP SOURCE
Following figure is a state diagram
NMI/Reset/IRQ Vector Program ROM Bank #1
STANDBY
IOEF Port Change TIMER 0 Overflow T16Hz ( 4Hz /8Hz /16Hz /32Hz ) T2 Hz ( 2Hz /1Hz )
$FFFA $FFFF
NMI/Reset/IRQ Vector
u eak W
po
ru
5.2. ROM Area
SPL31A is a ROM based micro-controller with 220 dots LCD driver. The large ROM space can be defined as a program ROM, LCD font and audio data continuously without any limitation. To
HALT
State Diagram of SPL31A
access the higher bank ROM area, user can program the BANK SELECT register ($07) to 1, then fetch the data from address $8000 to $FFFF. After the chip is awakened from halt/standby state, CPU will continue to execute the next instruction. will not be changed by wake-up. The RAM and I/O status
5.3. Operating States
The SPL31A provides three operating states: standby, halt, and operating state. Following table shows the differences between the three operating states.
5.4. Time-Base-Setting Register
Writing to TIME-SETTING register can program the time source of CPU wake-up and interrupt. For example, the programmer can change 2Hz wake-up and interrupt into 1Hz wake-up and interrupt
Operating CPU 32768 oscillator LCD driver ON ON ON
Halt OFF ON ON/OFF
Standby OFF OFF OFF
by writing 80H into $0A. Thus, the system will wake up to service every second. Also,
T16Hz (one of counter`s clock source and wake-up & interrupt) can be one of 4Hz, 8Hz, 16Hz or 32Hz by setting bit0 and bit1 of TIME-SETTING register ($0A). At power on state, the default
In
operating
state,
all
modules
(CPU,
32768
oscillator,
timer/counter, LCD driver...) are activated.
The halt/standby
value of T16Hz is 4Hz and T2Hz is 2Hz.
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SPL31A
5.5. Timer/Counter
SPL31A contains two 16-bit timer/counters, TM0 and TM1 respectively. up-counters. In the timer mode, TM0 and TM1 are reloadable When the timer overflows from $FFFF to $0000, The timer will count continuously. If TM0 is specified as a counter, the user can After the reset the counter by loading 0 into register $10 and $11 and loading 0 into the counter by writing any data to $12. counter is activated, the counter's value can also be read from above registers ($10 and $11) and the read instruction will not affect the counter's value or reset it.
the carry signal will generate the INT signal if the corresponding bit is enabled in INT ENABLE register ($0D). automatically reload the value assigned by the program and up The clock source of the timer/counter are selected as the following: Timer/Counter Address $0010 16-BIT Timer TM0 16-BIT Counter $0011 $0012 $0010 $0011 $0012 $0013 TM1 16-BIT Timer $0014 $0015 Mode Select Register $000B Clock Source
R-oscillator Output, the CARRY of timer 1 Clock source A: IOCD0, R-oscillator Output, VDD, 32768Hz. Clock source B: IOCD1, VDD, T16Hz, 128Hz.
Note: T16Hz can be one of 4Hz, 8Hz, 16Hz and 32Hz by setting $0A (time-setting register)
R-oscillator Output, 32768 Hz Select TM0 & TM1 configuration
5.6. Speech and Melody
Since SPL31A can provide a large ROM size and wide CPU operation speed, it is suitable for speech and melody synthesis. For speech synthesis, this chip can provide INT for precise sampling frequency. Users can record or synthesize the sound The sound can be played and digitize the data into the ROM.
5.8. Voltage Doubler/Regulator
To get the best LCD quality, the LCD supply voltage should not change with the system power. The SPL31A provides a robust Users can get and adjustable (16-level) LCD supply voltage. reference voltage (program $16).
desired VLCD to fit specific LCD panels by changing the output The available VLCD voltage range are summarized as the following table: Bias 1/2 bias 1/3 bias Min. VLCD ($16 = 00h) 2.0V 3.0V Max. VLCD ($16 = 0Fh) 4.0V 6.0V
back in the sequence designed by the internal user's program. Several algorithms are recommended for high fidelity and good compression of sound: such as PCM and ADPCM. synthesis, SPL31A provides dual tone mode. For melody Once in the dual
tone mode, users only need to program the tone frequency of each channel by writing to timer/counter TM0 and TM1, and set the envelope of each channel. The hardware will toggle the tone wave automatically without users' care.
Note1: If the LCD display is uneven with a large panel load, connect a resistor between the VDD1 pin and ground is suggested. Note2: To make sure the chip work properly, the following equation must be satisfied. Min. (VLCD) > VDD, Otherwise, VDD will change the VLCD.
5.7. LCD Controller/Driver
SPL31A contains a LCD controller and driver for 220dots LCD display. Users can set the LCD configuration (bias, duty, display Once the LCD mode) by writing LCD control register ($18). filling the LCD buffer with appropriate data.
5.9. PWM Output
Internally, SPL31A has one pair of PWM outputs supporting two sound channels. individually. circuit. Each channel can be set to play speech or tone SPL31A uses Pulse Width Modulation that is able to
configuration is initialized, the desired pattern can be displayed by The LCD driver can still operate during halt mode by keeping 32768 oscillator running. Furthermore, programmer can turn off the LCD display through LCD control register for power saving. bias are available from the LCD driver. The LCD driver in 1/2 or 1/3 SPL31A is designed to fit most LCD's specifications. duty can be programmed as 1/2, 1/3, 1/4 or 1/5 duty. (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 6
drive speaker or buzzer directly without any buffer or amplification
5.10. Low Voltage Reset
The SPL31A provides a low voltage reset function. VDD is lower than 2.3V. AUG. 10, 2001 Version: 1.2 The system will enter into LVRST state if and only if the power supply voltage
Meanwhile, The display
SPL31A
5.11. Watchdog Timer (WDT)
An on chip watchdog timer is available on SPL31A. The WDT is If the designed for recovering from system abnormal operation. system after 1 second.
5.13. Mask Options 5.13.1. 32768 crystal oscillator
1). X'TAL 2). R-oscillator
system is hanged, WDT will generate a system reset to restart If WDT is enabled, the WDT should be The WDT cleared every two seconds to avoid accidental reset.
5.13.2. Low voltage detect
1). 2.4V 2). 2.6V
can be cleared by writing the specified value 0FH to port $0F. Note that the WDT only works when 32768 Hz clock is available.
5.12. Low Voltage Detect
Furthermore, a Low Voltage Detect function is built in SPL31A. Once, the control register $17 bit7 is set to 1 (enable), the programmer can compare VDD voltage level with reference voltage 2.4V/2.6V from reading $17 bit0.
Note1: 50us delay time is recommended for voltage detect circuit stabilization. Note2: Be sure to turn off voltage detect circuit if not needed to minimize power consumption.
5.13.3. SEG[43:41] can be optioned to IOEF[7:5]
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AUG. 10, 2001 Version: 1.2
SPL31A
6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
Symbol V+ VIN TA TSTO
Ratings < 7.0V -0.5V to V+ + 0.5V 0 to +60 -50 to +150
For normal operational
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
6.2. DC Characteristics (VDD = 3.0V, TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Symbol VDD IOP ISTBY IOH Audio output current IOL Input High Level Input Low Level Output High I Output Sink I VIH VIL IOH IOL Limit Min. 2.4 2.0 Typ. 0.8 -50 -90 60 110 -2.0 2.5 Max. 3.6 1.0 0.8 Unit V mA A mA Test condition For 2-battery application VDD = 3.0V, FCPU = 600KHz VDD = 3.0V VDD = 3.0V, VOH = 2.5V VDD = 3.0V, VOH = 2.0V VDD = 3.0V, VOL = 0.5V VDD = 3.0V, VOL = 1.0V VDD = 3.0V VDD = 3.0V VDD = 3.0V, VOH = 2.4V VDD = 3.0V, VOL = 0.8V
mA V V mA mA
6.3. DC Characteristics (VDD = 4.5V, TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I Output Sink I Symbol VDD IOP ISTBY IOH IOL VIH VIL IOH IOL 3.0 Limit Min. 3.6 Typ. 1.6 -100 70 -2.0 2.5 Max. 5.5 1.0 0.8 Unit V mA A mA mA V V mA mA Test condition For 3-battery application VDD = 4.5V, FCPU = 600KHz VDD = 4.5V VDD = 4.5V, VOH = 3.5V VDD = 4.5V, VOL = 0.8V VDD = 4.5V VDD = 4.5V VDD = 4.5V, VOH = 3.5V VDD = 4.5V, VOL = 0.8V
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SPL31A
6.4. The Relationships between the ROSC and the FCPU 6.4.1. VDD = 3.0V, TA = 25 C
3
6.0
o
6.5. The Relationships between the FCPU and the IOP
VDD = 4.5V I OP ( m A ) 2
F OSC ( MHz )
4.0
1 VDD = 3V
2.0
0 0 2 F OSC ( MHz )
0 200 400 Rosc ( Kohms ) 600 800
4
6
0.0
6.6. The Relationships between the FCPU and the VDD 6.4.2. VDD = 4.5V, TA = 25 oC
6.0
6 F OSC ( MHz ) 4 2 0
Rosc = 51 Kohms
F OSC ( MHz )
4.0
Rosc = 360 Kohms
2.0
2
3
4 VDD ( Volts )
5
0.0 0 200 400 Rosc ( Kohms ) 600 800
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SPL31A
Bias Circuit
1/2 Bias 0.1 F IOCD3 IOCD2 IOCD1 IOCD0 0.1 F SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 AUDN AVDD AUDP AVSS RESET X32I X32O 0.1 F VDD1 VLCD CUP1 CUP2 1/3 Bias VDD1 VDD2 VLCD CUP1 CUP2 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43
I/O
I/O
DEVICE
VDD
8 ~ 64
RESET
20P
0.1 F
32768Hz
VSS VDD2 CUP2 CUP1 VDD1 VLCD IOEF4 IOEF3 IOEF2 IOEF1 IOEF0 COM4 COM3 COM2 COM1 COM0 TEST
Bias Circuit
I/O
SEGs [ 43:0 ]
7. APPLICATION CIRCUITS
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LCD Module
COMs [ 4:0 ]
10
SPL31A
ROSC VDD
20P
Rosc 0.1 F
VDD
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SPL31A Application Circuit
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Version: 1.2
SPL31A
8. PACKAGE/PAD LOCATIONS
8.1. PAD Assignment
Chip Size: 2270m x 3020m This IC substrate should be connected to VSS
Note1: Chip size included scribe line. Note2: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible.
8.2. Ordering Information
Product Number SPL31A-nnnnV-C
Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z).
Package Type Chip form
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AUG. 10, 2001 Version: 1.2
SPL31A
8.3. PAD Locations
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 PAD Name IOEF2 IOEF3 IOEF4 VDD SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 X -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -921 -784 -656 -538 -419 -301 -182 -64 55 173 292 410 529 647 766 884 Y 1395 1258 1116 885 765 645 525 405 285 165 45 -75 -195 -315 -435 -555 -675 -795 -915 -1035 -1168 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 -1295 PAD No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 PAD Name SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM4 COM3 COM2 COM1 COM0 VLCD VDD1 CPU1 CPU2 VDD2 TEST X32O X32I RESET ROSC VSS IOCD0 IOCD1 IOCD2 IOCD3 AVSS AUDP AVDD AUDN IOEF0 IOEF1 X 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 1021 884 766 647 529 410 292 173 55 -64 -182 -301 -419 -538 -656 -784 Y -1295 -1168 -1035 -908 -781 -654 -527 -400 -273 -146 -19 108 235 362 489 616 743 870 997 1124 1258 1395 1395 1395 1395 1395 1395 1395 1395 1395 1395 1395 1395 1395 1395 1395 1395
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SPL31A
9. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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AUG. 10, 2001 Version: 1.2
SPL31A
10. REVISION HISTORY
Date NOV. 17, 1999 SEP. 22, 2000 OCT. 19, 2000 APR. 30, 2001 Revision # 0.1 0.2 1.0 1.1 Original OSC Resistor Typ. 220K -> 177K Delete "PRELIMINARY" 1. Correct Min. (VLCD) - VDD > -0.5 to Min. (VLCD) > VDD 2. Renew to a new document format AUG. 10, 2001 1.2 1. Update "6. ELECTRCIAL SPECIFICATIONS" 2. Correct chip size 3. Add Note1 in the "8.1 PAD Assignment" 4. Renew to a new document 8-9 11 11 5 8 Description Page
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